A delay fault diagnosis of a semiconductor integrated circuit includes a technique of specifying a fault spot by using the information of fail/pass of a test and the fault dictionary.
Usually, a scan test method is used for the test. In the scan test method, a scan chain in which flip flops (hereinafter, referred to as FF) are connected in series is built into a semiconductor integrated circuit, and the test is carried out. A test pattern is input to the scan chain from an input terminal, and the test pattern is then propagated to a combinational circuit unit by applying a clock. The response pattern propagated to the combinational circuit unit is supplemented by the FF and is read out to an output terminal from the scan chain, and the signal level thereof is monitored by a tester. Then, the monitored response pattern and an expected value precalculated and stored in a memory of the tester are compared to each other, and it is determined as a pass if they match and determined as a fail if not. The expected value is calculated for all the FFs which make up the scan chain, and therefore, information as to which FF is determined as a pass or a fail can also be obtained. A series of these operations is executed for every test pattern, and the FF determined as a pass is referred to as a pass FF relating to the test pattern, and the FF determined as a fail is referred to as a fail FF relating to the test pattern.
The fault dictionary is obtained by a logic simulation using a computer as to which FF fails or passes for each applied test pattern when the fault exists in the semiconductor integrated circuit. When the FF fails, it means that the influence of the fault propagates to the FF and can be monitored by the tester. Also, when the FF passes, it means that the influence of the fault cannot be monitored. In the fault dictionary, a spot where a fault model is assumed is referred to as a fault assumption. Hence, the information contained in the fault assumption is a spot where the fault is assumed and an assumed fault model. The fault dictionary stores the information of pass/fail of all the FFs for every fault assumption.
In the fault diagnosis using the fault dictionary, the pass/fail information of all the FFs monitored by the tester for every test pattern and the pass/fail information of all the FFs of the fault assumption stored in the fault dictionary are collated, and the matched fault assumption is taken as a fault candidate. Even if not completely matched, the fault candidate having the high possibility of being a real fault is specified by weighting the matching degree.
In a delay fault diagnosis, the fault dictionary is prepared by assuming a delay fault. The delay fault means that a signal does not propagate within a “set time” and causes a logical malfunction in the semiconductor integrated circuit. Usually, a clock cycle determined by a clock operation frequency of the semiconductor integrated circuit corresponds to the “set time”. Hence, a logical state, in which the transition of a signal generated at a specific logical node delays due to the influence of the fault and therefore the propagation does not arrive at the FF to be observed within the set time, so that the signal transition is not observed at the FF, is modeled as the fault model of the delay fault. More specifically, a fall fault in which the logic level is left at H at the spot where the logic level of the signal makes a transition from H (high level) to L (low level) and a rise fault in which the logic level is left at L at the spot where the signal makes a transition from L to H are handled.
U.S. Pat. No. 7,516,383 (Patent Document 1) is cited as an example that describes the delay fault diagnosis. In the fault diagnosis technique disclosed in Patent Document 1, first, a trace is performed from the fail FF to the input side, thereby narrowing down the fault candidate. Then, the delay fault is assumed for the narrowed-down candidate, and the logical simulation is performed for the candidate. Finally, the pass/fail information obtained by the simulation and the pass/fail information by the test are collated, thereby specifying the fault spot.